1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to a field effect device having a polycrystalline silicon channel.
2. Description of the Prior Art
CMOS static random access memories (SRAM) are increasingly used in the electronics industry due to their combination of speed, low power, and no requirement for refresh. A CMOS SRAM cell is built around a cross-coupled latch and accessed by, typically, 2 control gates for a standard SRAM cell. Four control gates are used to access the cell for 2-port memory devices.
The basic SRAM cell can be formed using cross-coupled CMOS inverters, having 2 each N-channel and P-channel transistors. To conserve physical layout space, the P-channel transistors are often replaced with resistive loads. Typical loads include a polycrystalline silicon resistor, and 2 back-to-back polycrystalline silicon diodes. An example of the latter is described in co-pending U.S. patent application Ser. No. 298,530, filed Jan. 18, 1989, titled METHOD FOR FABRICATING SEMICONDUCTOR CIRCUITS, which has been incorporated by reference hereinto. Resistive loads of either type are formed to have a very high resistance in order to reduce power consumption by the cell.
Use of a P-channel transistor as the load for the SRAM cell results in a cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the P-channel transistors can provide a higher drive current than high resistance devices. Also, use of P-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating P-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs.
It would be desirable to provide an SRAM cell which combined the advantages of P-channel loads with the cell layout area requirements of resistive load cells. It would be further desirable to provide a field effect device load, suitable for use with an SRAM cell, which provides increased current drive over resistive loads, and which provides a high OFF resistance.